//******************************************************************************
// Copyright(c) 2013, Hangzhou Guanglu Electronics Co., Ltd.
// All rights reserved
//
// Project Name    :    OLB_10G
// Filename        :    transceiver_top.v
// Designer        :
// Email        :
// Date            :    2013-05-18
// Version        :    1.0
//
// Module Name    :    TRANSCEIVER_TOP
// Description    :    TOP level of ONE TX & ONE RX TO S19250
//
//
// Called by    :    none
//
// Modification History`                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    
// -----------------------------------------------------------------------------
// 
//

// ***********************************************
// TIMESCALE
// ***********************************************
`timescale    1ns/100ps

// ***********************************************
// INCLUDE
// ***********************************************
`include    "defines.v"

// ***********************************************
// MARCO DEFINITIONs
// ***********************************************


// ***********************************************
// MODULE DEFINITION
// ***********************************************
module OLB_10G_TOP(
    input           ex_clk200m_p,
    input           ex_clk200m_n,
    output           CLK_FPGA_200M_P,
    output           CLK_FPGA_200M_N,
    
    output          FPGA_TO_S250_CLKP,
    output          FPGA_TO_S250_CLKN,
    
    input   [19:0]  OLB_A,
    inout   [15:0]  OLB_D,
    output          OUT6_CPLD_CLK_FPGA,
    output          OUT5_CPLD_CLK_FPGA,
    input           CLK2OUT124_P,
    input           CLK2OUT124_N,
//  input           CK2OUT_TO_FPGA_P,
//  input           CK2OUT_TO_FPGA_N,
    input           CLK_FPGA,
    
//    input           OLB_RD_WR,
//    input           OLB_CS,
    output          OLB_INT,

    output          OH_OLB_TO_OAM_FPGA,
    input           OH_OAM_TO_OLB_FPGA,
    output          TESTFPGALED1,
    output          TESTFPGALED2,
    output          TESTFPGALED3,
    output          TESTFPGALED4,

    input           TP1,
    input           TP2,
    input           TP3,
    input           TP4,
    input           TP5,
    input           TP6,
    //input           TP7,
    input           TP8,
    input           TP9,
    input           TP10,
    output           TP11,
    output           TP12,
    input           TP13,
    output           TP14,
    input           TP61,
    input           TP60,

    inout           I2C1_SDA_TEMP,
    output          I2C1_SCL_TEMP,
    input           ALT_TEMP,
    inout           INVENTORY_DATA_FPGA,

    inout           SFP_IIC_SDA0_FPGA,
    output          SFP_IIC_SCL0_FPGA,

    input   [16:1]  FPGA_CPLD,
    input   [8:1]   FPGA_TO_CPLD_ADD,

//    input           CLK_FPGA_3P,
//    input           CLK_FPGA_3N,

//    input           CLK_FPGA_4P,
//    input           CLK_FPGA_4N,
    
    
//    input           CLK_FPGA_2P,
//    input           CLK_FPGA_2N,
    input           CLK_FPGA_1P,
    input           CLK_FPGA_1N,

    input           RDWR_B,
    input           CSI_B,

    
    input   [15:0]  S250_TO_FPGA_DATP,
    input   [15:0]  S250_TO_FPGA_DATN,

    input           S250_TO_FPGA_POCLK_P,
    input           S250_TO_FPGA_POCLK_N,

    output  [15:0]  FPGA_TO_S250_DATP,
    output  [15:0]  FPGA_TO_S250_DATN,

    output          FPGA_TO_S250_PICLK_P,
    output          FPGA_TO_S250_PICLK_N,
	
    input           FPGA_TO_S250_PCLK_P,
    input           FPGA_TO_S250_PCLK_N,

///    output  [3:0]   DATA_OLB_TO_XC2P,
///    output  [3:0]   DATA_OLB_TO_XC2N,
///    input   [3:0]   DATA_XC2_TO_OLBP,
///    input   [3:0]   DATA_XC2_TO_OLBN,
/// 
///    input           MGTREFCLK0_112P,
///    input           MGTREFCLK0_112N,
///
///    output  [3:0]   DATA_OLB_TO_XC1P,
///    output  [3:0]   DATA_OLB_TO_XC1N,
///    input   [3:0]   DATA_XC1_TO_OLBP,
///    input   [3:0]   DATA_XC1_TO_OLBN,
/// 
///    input           MGTREFCLK0_113P,
///    input           MGTREFCLK0_113N


  // backplane transceiver signals
    input                              TRSV_Q0_RFCLK_P,
    input                              TRSV_Q0_RFCLK_N,
    input                              TRSV_Q1_RFCLK_P,
    input                              TRSV_Q1_RFCLK_N,

    input                              TRSV_AFE_0_RXDATA_P,
    input                              TRSV_AFE_0_RXDATA_N,
    output                             TRSV_AFE_0_TXDATA_P,
    output                             TRSV_AFE_0_TXDATA_N,

    input                              TRSV_AFE_1_RXDATA_P,
    input                              TRSV_AFE_1_RXDATA_N,
    output                             TRSV_AFE_1_TXDATA_P,
    output                             TRSV_AFE_1_TXDATA_N,

    input                              TRSV_AFE_2_RXDATA_P,
    input                              TRSV_AFE_2_RXDATA_N,
    output                             TRSV_AFE_2_TXDATA_P,
    output                             TRSV_AFE_2_TXDATA_N,

    input                              TRSV_AFE_3_RXDATA_P,
    input                              TRSV_AFE_3_RXDATA_N,
    output                             TRSV_AFE_3_TXDATA_P,
    output                             TRSV_AFE_3_TXDATA_N,

    input                              TRSV_AFE_4_RXDATA_P,
    input                              TRSV_AFE_4_RXDATA_N,
    output                             TRSV_AFE_4_TXDATA_P,
    output                             TRSV_AFE_4_TXDATA_N,

    input                              TRSV_AFE_5_RXDATA_P,
    input                              TRSV_AFE_5_RXDATA_N,
    output                             TRSV_AFE_5_TXDATA_P,
    output                             TRSV_AFE_5_TXDATA_N,

    input                              TRSV_AFE_6_RXDATA_P,
    input                              TRSV_AFE_6_RXDATA_N,
    output                             TRSV_AFE_6_TXDATA_P,
    output                             TRSV_AFE_6_TXDATA_N,

    input                              TRSV_AFE_7_RXDATA_P,
    input                              TRSV_AFE_7_RXDATA_N,
    output                             TRSV_AFE_7_TXDATA_P,
    output                             TRSV_AFE_7_TXDATA_N,

  // the system timing and control signals
    input                              SYS_CLK_FP1_OLB_FPGA,
    input                              SYS_CLK_FP2_OLB_FPGA,

    input                              XC_ACT1_CPLD,
    input                              XC_ACT2_CPLD,
    output                             LINE_OLB_CLK_1_FPGA,
    output                             LINE_OLB_CLK_2_FPGA,
    output                             LINE_OLB_CLK_FP_1_FPGA,
    output                             LINE_OLB_CLK_FP_2_FPGA
 );

// ***********************************************
// INTERNAL SIGNAL
// ***********************************************
    


wire    [15:0]      CHNN0_DATA_TX_P;
wire    [15:0]      CHNN0_DATA_TX_N;
wire                CHNN0_CLOCK_TX_P;
wire                CHNN0_CLOCK_TX_N;
//wire    [15:0]      CHNN1_DATA_TX_P;
//wire    [15:0]      CHNN1_DATA_TX_N;
//wire                CHNN1_CLOCK_TX_P;
//wire                CHNN1_CLOCK_TX_N;
//wire    [15:0]      CHNN2_DATA_TX_P;
//wire    [15:0]      CHNN2_DATA_TX_N;
//wire                CHNN2_CLOCK_TX_P;
//wire                CHNN2_CLOCK_TX_N;
//wire    [15:0]      CHNN3_DATA_TX_P;
//wire    [15:0]      CHNN3_DATA_TX_N;
//wire                CHNN3_CLOCK_TX_P;
//wire                CHNN3_CLOCK_TX_N;
   
//wire                d_buff_ready;    
//wire                d_dvt;
//wire                d_sop_outt;
//wire                d_eop_outt;
//wire                d_errt;
//wire    [3:0]       d_modt;
//wire    [127:0]     d_doutt;
//wire                ddvout;

wire                osc_200m;
wire                sdh_622clk;

wire                sfi_refclk_out_0_p;
wire                sfi_refclk_out_0_n;

(* keep = "TRUE" *)wire                        clk50m;
//wire                sfi_refclk_out_1_p;
//wire                sfi_refclk_out_1_n;
//wire                sfi_refclk_out_2_p;
//wire                sfi_refclk_out_2_n;
//wire                sfi_refclk_out_3_p;
//wire                sfi_refclk_out_3_n;   
wire	[15:0]		mpi_par_keep;
wire    [3:0]       led;
// ***********************************************
// PARAMETER
// ***********************************************


///   assign  FPGA_TO_S250_DATP[15:0]   = S250_TO_FPGA_DATP;

// ***********************************************
// INTERNAL SIGNAL
// ***********************************************
//CLOCK DEFINITION

wire    clk125m_sys;
wire    clk125m;

wire    [7:0]   RXN_IN;
wire    [7:0]   RXP_IN;
wire    [7:0]   TXN_OUT;
wire    [7:0]   TXP_OUT;
reg		clk_test;
reg		clk_test_t;

wire            a_sfi4_rclkg;
wire            a_sfi4_tclk;
wire	[15:0]  DATA_RX_BUF;
reg				clk_test1;
reg				clk_100m;
//************************************************** 
//
//**************************************************                          

// IBUFDS #(.DIFF_TERM("TRUE"), .IOSTANDARD("LVDS_25")) RX_CLK_IN(.O(CLOCK_RX_BUF), .I(S250_TO_FPGA_POCLK_P), .IB(S250_TO_FPGA_POCLK_N));
//always @(posedge CLOCK_RX_BUF or posedge reset_h) 
//begin 
//	 if (reset_h == 1'b1)
//    begin
//		  clk_test1 <= 1'b0;
//    end
//    else
//    begin
//		  clk_test1 <= ~clk_test1;
//    end
//end

//assign TESTFPGALED1 = clk_test1;
assign TESTFPGALED1 = ~c200m_lda;
assign TESTFPGALED2 = ~c200m_ldb;
assign TESTFPGALED3 = clk50m;
assign TESTFPGALED4 = clk50m;
 

assign	LINE_OLB_CLK_FP_1_FPGA = SYS_CLK_FP1_OLB_FPGA;
assign	LINE_OLB_CLK_FP_2_FPGA = SYS_CLK_FP2_OLB_FPGA;

assign	OUT6_CPLD_CLK_FPGA = LINE_OLB_CLK_1_FPGA;
assign	OUT5_CPLD_CLK_FPGA = LINE_OLB_CLK_1_FPGA;

assign	OH_OLB_TO_OAM_FPGA = OH_OAM_TO_OLB_FPGA;
    
assign	I2C1_SCL_TEMP = I2C1_SDA_TEMP;

assign	SFP_IIC_SCL0_FPGA = SFP_IIC_SDA0_FPGA;


    assign          LINE_OLB_CLK_1_FPGA = 1'b0;
    assign          LINE_OLB_CLK_2_FPGA = 1'b0;
	
assign TP12 = 	clk_test;
assign TP11 = clk_test_t;
always @(posedge a_sfi4_rclkg or posedge reset_h) 
begin 
	 if (reset_h == 1'b1)
    begin
		  clk_test <= 1'b0;
    end
    else
    begin
		  clk_test <= ~clk_test;
    end
end
	
always @(posedge a_sfi4_tclk or posedge reset_h) 
begin 
	 if (reset_h == 1'b1)
    begin
		  clk_test_t <= 1'b0;
    end
    else
    begin
		  clk_test_t <= ~clk_test_t;
    end
end

///clk_155_to_19	U_clk_155_to_19 (
///	// Clock in ports
///  .RESET			(reset_h),
///  .CLK_IN1			(a_sfi4_rclkg),
///  // Clock out ports
///  .CLK_OUT1			(LINE_OLB_CLK_1_FPGA),
///  .CLK_OUT2			(LINE_OLB_CLK_2_FPGA),
///  // Status and control signals
///  
///  .LOCKED			()
/// );


//IBUFGDS Ut_CLK155M_IN(
//  .O(clk155m_test), 
//  .I(CK2OUT_TO_FPGA_P), 
//  .IB(CK2OUT_TO_FPGA_N)

//  );

    
///IBUFGDS U4_CLK155M_IN(
///    .O(clk155m_4), 
///    .I(CLK_FPGA_4P), 
///    .IB(CLK_FPGA_4N)
///
///    );

IBUFGDS U_CLK155M_124(
    .O(clk155m_124), 
    .I(CLK2OUT124_P), 
    .IB(CLK2OUT124_N)

    );

OBUFDS  U_OBUFDS_155M_CLOCK
	(
	.O(FPGA_TO_S250_CLKP), 
	.OB(FPGA_TO_S250_CLKN), 
	.I(clk155m_124)
	);
    
    
    
clk_25M_TO_200M     U_clk_25M_TO_200M (
// Clock in ports
  .RESET        (reset_h),
  .CLK_IN1      (CLK_FPGA),
  // Clock out ports
  .CLK_OUT1     (CLK_200M),
  .LOCKED       (c200m_lda)
 );

OBUFDS  U_OBUFDS_200M_CLOCK
	(
	.O(CLK_FPGA_200M_P), 
	.OB(CLK_FPGA_200M_N), 
	.I(CLK_200M)
	);
     

IDELAYCTRL RX_IDELAYCTRL(.RDY(), .REFCLK(delay_200m), .RST(reset_h));   //  

clkin200_200_125    U_clkin200_200_125 (
    .RESET          (reset_h),
  
  // Clock in ports
  .CLK_IN1_P        (ex_clk200m_p),
  .CLK_IN1_N        (ex_clk200m_n),
  // Clock out ports
    .CLK_OUT1       (delay_200m),
    .CLK_OUT2       (clk125m),
    .CLK_OUT3       (clk50m),
  // Status and control signals
    .LOCKED         (c200m_ldb)
 );
	

///IBUFGDS U3_CLK155M_IN(
///    .O(clk155m_sys), 
///    .I(CLK_FPGA_3P), 
///    .IB(CLK_FPGA_3N)
///
///    );

assign TP14 = clk_100m;

always @( posedge reset_h or posedge CLK_200M ) begin
    if ( reset_h==1'b1 )
		clk_100m            <= 1'b0;
    else begin
		clk_100m <= ~clk_100m;
    end
end

	
///assign rst_fpga_n = ~rst_fpga;
///assign FPGA_CPLD1  = 1'b0;
///assign FPGA_CPLD2  = 1'b0; 
///assign FPGA_CPLD3  = 1'b0; 
///assign FPGA_CPLD4  = 1'b0; 
///assign FPGA_CPLD5  = 1'b0; 
///assign FPGA_CPLD6  = CPLD_TO_S250_SDO; 
///assign FPGA_CPLD7  = CPLD_TO_S250_CS; 
///assign FPGA_CPLD8  = CPLD_TO_S250_SCK; 
///assign FPGA_CPLD9  = CPLD_TO_S250_SDI; 
///assign FPGA_CPLD10 = s19250_data_cnt[6]; 
///assign FPGA_CPLD11 = s19250_data_cnt[5]; 
///assign FPGA_CPLD12 = 1'b0; 
///assign FPGA_CPLD13 = OLB_RD_WR; 
///assign FPGA_CPLD14 = CLK_CPLD; 
///assign FPGA_CPLD15 = rst_fpga_n; 
///assign FPGA_CPLD16 = fpga_cs_n;
	
	
assign  reset_h = ~ex_reset_n;
assign  ex_reset_n = FPGA_CPLD[15];
assign	OLB_CS = ~FPGA_CPLD[16];
assign	OLB_RD_WR = FPGA_CPLD[13];
//########################################################################

// CPU interface signals to I/O
wire[15:0]                                  CPU_ADDRESS;
wire                                        CPU_CSN;
wire                                        CPU_WRN;
wire[15:0]                                  CPU_DATA;

// GMPI bus signals
(* keep = "TRUE" *) wire                    GMPI_CLK;
(* keep = "TRUE" *) wire[15:0]              GMPI_A;
(* keep = "TRUE" *) wire[15:0]              GMPI_WD;
(* keep = "TRUE" *) wire                    GMPI_WE;
(* keep = "TRUE" *) wire                    GMPI_CS_BKP;
(* keep = "TRUE" *) wire[15:0]              GMPI_RD_BKP;

// global control signals and timing signals
wire                                        XC_0_FP;
wire                                        XC_1_FP;
wire                                        GTM_RESET;
wire                                        GTM_CLK155M;
(* keep = "TRUE" *) wire                    GTM_AUPP_FP8K;
(* keep = "TRUE" *) wire                    GTM_BKP_FP8K;






// ******************     Global Signals Generate          ******************//
assign   GTM_RESET         = !FPGA_CPLD;      // global reset drived by CPLD

// system clock 155m
IBUFGDS #(
    .DIFF_TERM("TRUE"),
    .IOSTANDARD("LVDS_25")
     ) 
INST_GTM_CLK155M_BUFG (
    .O(GTM_CLK155M), 
    .I(CLK_FPGA_1P), 
    .IB(CLK_FPGA_1N)
    );


  assign  XC_0_FP      = SYS_CLK_FP1_OLB_FPGA;
  assign  XC_1_FP      = SYS_CLK_FP2_OLB_FPGA;
STSC_TOP                                    INST_STSC_TOP(
   .GTM_RESET                               ( GTM_RESET ),
   .GTM_CLK155M                             ( GTM_CLK155M ),

   .XC_0_FP                                 ( XC_0_FP ),
   .XC_1_FP                                 ( XC_1_FP ),

   .GTM_AUPP_FP8K                           ( GTM_AUPP_FP8K ),
   .GTM_BKP_FP8K                            ( GTM_BKP_FP8K )
   );











  BUFG     GMPI_CLK_BUFG    ( .O( GMPI_CLK ),       .I( clk_100m ));
  assign   CPU_ADDRESS[15:0] = OLB_A[15:0];
  assign   OLB_D[15:0]       = CPU_DATA[15:0];
  assign   CPU_CSN           = FPGA_CPLD[16];   // CSN drived by CPLD
  assign   CPU_WRN           = FPGA_CPLD[13];   // WRN drived by CPLD
  assign   OLB_INT           = 1'b1;            // disable the interrupt

CPU_INTERFACE                               INST_CPU_INTERFACE(
   .GTM_RESET                               ( GTM_RESET ),

   .CPU_ADDRESS                             ( CPU_ADDRESS[15:0] ),
   .CPU_CSN                                 ( CPU_CSN ),
   .CPU_WRN                                 ( CPU_WRN ),
   .CPU_DATA                                ( CPU_DATA[15:0] ),

   .GMPI_CLK                                ( GMPI_CLK ),
   .GMPI_A                                  ( GMPI_A[15:0] ),
   .GMPI_WD                                 ( GMPI_WD[15:0] ),
   .GMPI_WE                                 ( GMPI_WE ),
   .GMPI_CS_BKP                             ( GMPI_CS_BKP ),
   .GMPI_RD_BKP                             ( GMPI_RD_BKP[15:0] )
   ) ;


/*OLB_REG U_OLB_REG(
// input
    .clk_cpld               (clk155m_sys),
    .reset_h                (reset_h),
    
    .cpld_cs                (OLB_CS),
    .w_r                    (OLB_RD_WR),
	.cpld_addr				(OLB_A[19:0]),
    
    .adio                   (OLB_D[15:0]),
    
    .int                    (OLB_INT),
    
    .fpga_data_empty_flg        (1'b0),

    .fpga_nstatus           (1'b0),
    .fpga_conf_done         (1'b0),

    .fpga_int               (1'b0),
    .cpld_int               (1'b0),
    .glb_int                (1'b0),


	.oe_test				(oe_test),
    .c3b_si_to_cpld         (1'b0),
    .c2b_si_to_cpld         (1'b0),
    .c1b_si_to_cpld         (1'b0),
    .c1a_si_to_cpld         (1'b0),
    .c2a_si_to_cpld         (1'b0),
    .lol_si_to_cpld         (1'b0),
    .int_alm_si_to_cpld     (1'b0),

    .mpi_par_keep           (mpi_par_keep[15:0]),
    .cs0_si_to_cpld         (1'b0),
    .cs1_si_to_cpld         (1'b0),
    
    
    .soft_rst               (),
	.rst_fpga				(),           // rst_fpga_logic
	.rst_cfg				(),
    .rst_si5369             (),
    .cksel_reg              (),
    .cs0_c3a                (),
    .cs1_c4a                (),
    
    .fpga_cfg_mode          (),
    .fpga_init              (),
    .flg_a_set              (),

    .fpga_data_a            (),
    .fpga_data_b            (),
    .fpga_data_c            (),
    .fpga_data_d            (),

    .flg_si_set             (),
    .si5369_data_empty_flg  (1'b0),
    .si5369_data_a          (),
    .si5369_data_r          (16'h0000),
    
    .switch_sel3_cpld       (),
    .switch_sel2_cpld       (),
    .switch_sel1_cpld       (),
    .switch_sel0_cpld       (),
    .s155_622               (),
    .run                    (),
    .run1                   (),
    .active_1               (),
    .active_2               (),
    .active_3               (),
    .active_4               (),
    .alm                    (),
    .alm_1                  (),
    .alm_2                  (),
    .alm_3                  (),
    .alm_4                  (),
    
	 .test1						(),
	 .test2						()
);*/


//########################################################################
reg     [27:0]      sfi4_rst_cnt;
reg                 sfi4_rst;
wire    [63:0]      sfi4_rdata;
wire    [63:0]      sfi4_tdata;
wire    [63:0]      core_rdata;
wire    [63:0]      core_tdata;
wire    [3:0]       frm10g_per_b1count;
wire    [15:0]      frm10g_fas_regkeep;
(* keep = "TRUE" *)wire    [63:0]      oh2frm_tdata;
(* keep = "TRUE" *)wire    [2:0]       oh2frm_fcnt8;
(* keep = "TRUE" *)wire    [8:0]       oh2frm_fcnt270;
(* keep = "TRUE" *)wire    [3:0]       oh2frm_fcnt9;
(* keep = "TRUE" *) wire                frm2oh_lof;
(* keep = "TRUE" *) wire                frm2oh_oof;
(* keep = "TRUE" *) wire    [2:0]       frm2oh_fcnt8;
(* keep = "TRUE" *) wire    [8:0]       frm2oh_fcnt270;
(* keep = "TRUE" *) wire    [3:0]       frm2oh_fcnt9;
(* keep = "TRUE" *) wire    [63:0]      frm2oh_rdata;

(* keep = "TRUE" *)wire                          BKP_TXFP8K;
(* keep = "TRUE" *)wire[15:0]                    BKP_TXDATA_0;
(* keep = "TRUE" *)wire[15:0]                    BKP_TXDATA_1;
(* keep = "TRUE" *)wire[15:0]                    BKP_TXDATA_2;
(* keep = "TRUE" *)wire[15:0]                    BKP_TXDATA_3;

(* keep = "TRUE" *)wire                          BKP_OUT_RXFP8K;
(* keep = "TRUE" *)wire[15:0]                    BKP_OUT_RXDATA_0;
(* keep = "TRUE" *)wire[15:0]                    BKP_OUT_RXDATA_1;
(* keep = "TRUE" *)wire[15:0]                    BKP_OUT_RXDATA_2;
(* keep = "TRUE" *)wire[15:0]                    BKP_OUT_RXDATA_3;

wire                         AUPP_FP8K;
wire[63:0]                   AUPP_DATA;
wire                         AUPP_SPE;
wire                         AUPP_J1;

always @(posedge CLK_200M or `RST_EDGE reset_h)
begin
		if(reset_h == `RST_VALUE)
			sfi4_rst_cnt[27:0] <= 28'h000_0000;
		else if(sfi4_rst_cnt[27:0] != 28'hfff_ffff)		
			sfi4_rst_cnt[27:0] <= sfi4_rst_cnt[27:0] + 1;
		else
		    sfi4_rst_cnt[27:0] <= 28'hfff_ffff;
end
always @(posedge CLK_200M or `RST_EDGE reset_h)
begin
		if(reset_h == `RST_VALUE)
			sfi4_rst <= 1'b0;
		else if(sfi4_rst_cnt[27:0] == 28'hfff_ffff)
		    sfi4_rst <= 1'b0;
		else if(sfi4_rst_cnt[27] == 1'b0)
			sfi4_rst <= 1'b0;
		else if(sfi4_rst_cnt[27] == 1'b1)
		    sfi4_rst <= 1'b1;
		else
			sfi4_rst <= 1'b0;
end				


SFI4_TOP UA_SFI4_TOP(
//  .RESET                              (reset_h),
    .RESET                              (sfi4_rst),

    .SFI4_TXDATA_P                      (FPGA_TO_S250_DATP[15:0]),
    .SFI4_TXDATA_N                      (FPGA_TO_S250_DATN[15:0]),
    .SFI4_TXCLK_P                       (FPGA_TO_S250_PICLK_P),
    .SFI4_TXCLK_N                       (FPGA_TO_S250_PICLK_N),

    .SFI4_RXDATA_P                      (S250_TO_FPGA_DATP[15:0]),
    .SFI4_RXDATA_N                      (S250_TO_FPGA_DATN[15:0]),
    .SFI4_RXCLK_P                       (S250_TO_FPGA_POCLK_P),
    .SFI4_RXCLK_N                       (S250_TO_FPGA_POCLK_N),
    
    .INTERFACE_TXCLK_P                  (FPGA_TO_S250_PCLK_P),
    .INTERFACE_TXCLK_N                  (FPGA_TO_S250_PCLK_N),

	.OSC_200M                           (delay_200m),
    .rxclk_sel                          (glb_sfi4_t2rloop),

    .SFI4_RCLK                          (sfi4_rclk),
    .SFI4_RDATA                         (sfi4_rdata[63:0]),
    .SFI4_TCLK                          (sfi4_tclk),
    .SFI4_TDATA                         (sfi4_tdata[63:0]),

    .SFI_MANUAL_DELAY_INC               (1'b0),
    .SFI_MANUAL_DELAY_DEC               (1'b0),
    .SFI_TRAINING_DONE                  (SFI_TRAINING_DONE),
    .SFI_IDELAY_READY                   (SFI_IDELAY_READY)
);


SFI_LOOP_CONTROL                        UA_SFI_LOOP_CONTROL(
   .RESET                               ( reset_h ),
   .SFI4_RCLK                           ( sfi4_rclk ),
   .SFI4_RDATA                          ( sfi4_rdata[63:0] ),
   .SFI4_TCLK                           ( sfi4_tclk ),
   .SFI4_TDATA                          ( sfi4_tdata[63:0] ),
   .CORE_RCLK                           ( sfi4_rclk ),
   .CORE_RDATA                          ( core_rdata[63:0] ),
   .CORE_TCLK                           ( GTM_CLK155M ),
   .CORE_TDATA                          ( core_tdata[63:0] ),
   
    .chnn_tx_pclk_p						(),
	.chnn_tx_pclk_n						(),

//   .MPI_SFI2SFI_LOOP                    (a_glb_sfi4_r2tloop),   // loop SFI4 Received data to transmit data
   .MPI_SFI2SFI_LOOP                    (1'b0),   // loop SFI4 Received data to transmit data
   .MPI_CORE2CORE_LOOP                  (glb_sfi4_t2rloop),   // loop core logic transmit data to received data
   .MPI_FIFO_CLEAR                      ( 1'b0 ),
   .MPI_ERROR_CLEAR                     ( 1'b0 ),
   .MPI_FIFO_FULL                       (  ),
   .MPI_FIFO_EMPTY                      (  )
);



  assign frm10g_fas_regkeep[15:0]    = 16'hffff;
FRM_TOP u_FRM_TOP(
        .RESET                  (rst),
  // interface to global cpu interface
        .FRM10G_SCRAME_EN       (1'b1),
        .FRM10G_FORCE_RX_LOF    (frm10g_force_rx_lof),
        .FRM10G_FORCE_RX_AIS    (frm10g_force_rx_ais),
        .FRM10G_FORCE_TX_AIS    (frm10g_force_tx_ais),
        .FRM10G_ALM_LOF         (frm10g_alm_lof),
        .FRM10G_ALM_OOF         (frm10g_alm_oof),
        .FRM10G_PER_B1COUNT     (frm10g_per_b1count[3:0]),
        .FRM10G_PER_B1PULSE     (frm10g_per_b1pulse),
        .FRM10G_FAS_REGKEEP     (frm10g_fas_regkeep[15:0]),
  
  // interface to sfi interface
        .FRM_SFI_RCLK_155M      (sfi4_rclk),
        .FRM_SFI_RDATA          (sfi4_rdata[63:0]),
        .FRM_SFI_TCLK_155M      (GTM_CLK155M),
        .FRM_SFI_TDATA          (core_tdata[63:0]),
  //
        .FRM_TOH_TDATA          (oh2frm_tdata),
        .FRM_TOH_FCNT8          (oh2frm_fcnt8),
        .FRM_TOH_FCNT270        (oh2frm_fcnt270),
        .FRM_TOH_FCNT9          (oh2frm_fcnt9),
  //
        .FRM_ROH_LOF            (frm2oh_lof),
        .FRM_ROH_OOF            (frm2oh_oof),
        .FRM_ROH_FCNT8          (frm2oh_fcnt8),
        .FRM_ROH_FCNT270        (frm2oh_fcnt270),
        .FRM_ROH_FCNT9          (frm2oh_fcnt9),
        .FRM_ROH_RDATA          (frm2oh_rdata)
);







AUPP_TOP                        INST_AUPP_TOP(
   .GTM_RESET                   ( rst ),
   .GTM_CLK155M52               ( GTM_CLK155M ),
   .GTM_AUPP_FP8K               ( GTM_AUPP_FP8K ),

   .FRM_IN_FP8K                 ( frm2oh_fcnt8[2:0]==3'd0 && frm2oh_fcnt270[8:0]==9'd0 && frm2oh_fcnt9[3:0]==4'd0 ),
   .FRM_IN_DATA                 ( frm2oh_rdata[63:0] ),
   .FRM_IN_RCLK                 ( sfi4_rclk ),

   .AUPP_OUT_FP8K               ( AUPP_FP8K ),
   .AUPP_OUT_DATA               ( AUPP_DATA[63:0] ),
   .AUPP_OUT_SPE                ( AUPP_SPE ),
   .AUPP_OUT_J1                 ( AUPP_J1 )
   );

//########################################################################



  assign  BKP_TXFP8K                  = AUPP_FP8K;
  assign  BKP_TXDATA_0[15:0]          = AUPP_DATA[63:48];
  assign  BKP_TXDATA_1[15:0]          = AUPP_DATA[47:32];
  assign  BKP_TXDATA_2[15:0]          = AUPP_DATA[31:16];
  assign  BKP_TXDATA_3[15:0]          = AUPP_DATA[15:0];


BKP_TOP                                          INST_BKP_TOP(
   .GTM_RESET                                    ( reset_h ),
   .GTM_CLK155M52                                ( GTM_CLK155M ),
   .GTM_BKP_FP8K                                 ( GTM_BKP_FP8K ),

   .GMPI_CLK                                     ( GMPI_CLK ),
   .GMPI_A                                       ( GMPI_A[7:0] ),
   .GMPI_WD                                      ( GMPI_WD[15:0] ),
   .GMPI_WE                                      ( GMPI_WE ),
   .GMPI_CS                                      ( GMPI_CS_BKP ),
   .GMPI_RD_BKP                                  ( GMPI_RD_BKP[15:0] ),


   .TRSV_IN_Q0_RFCLK_P                           ( TRSV_Q0_RFCLK_P ),
   .TRSV_IN_Q0_RFCLK_N                           ( TRSV_Q0_RFCLK_N ),
   .TRSV_IN_Q1_RFCLK_P                           ( TRSV_Q1_RFCLK_P ),
   .TRSV_IN_Q1_RFCLK_N                           ( TRSV_Q1_RFCLK_N ),

   .TRSV_AFE_0_RXDATA_P                          ( TRSV_AFE_0_RXDATA_P ),
   .TRSV_AFE_0_RXDATA_N                          ( TRSV_AFE_0_RXDATA_N ),
   .TRSV_AFE_0_TXDATA_P                          ( TRSV_AFE_0_TXDATA_P ),
   .TRSV_AFE_0_TXDATA_N                          ( TRSV_AFE_0_TXDATA_N ),

   .TRSV_AFE_1_RXDATA_P                          ( TRSV_AFE_1_RXDATA_P ),
   .TRSV_AFE_1_RXDATA_N                          ( TRSV_AFE_1_RXDATA_N ),
   .TRSV_AFE_1_TXDATA_P                          ( TRSV_AFE_1_TXDATA_P ),
   .TRSV_AFE_1_TXDATA_N                          ( TRSV_AFE_1_TXDATA_N ),

   .TRSV_AFE_2_RXDATA_P                          ( TRSV_AFE_2_RXDATA_P ),
   .TRSV_AFE_2_RXDATA_N                          ( TRSV_AFE_2_RXDATA_N ),
   .TRSV_AFE_2_TXDATA_P                          ( TRSV_AFE_2_TXDATA_P ),
   .TRSV_AFE_2_TXDATA_N                          ( TRSV_AFE_2_TXDATA_N ),

   .TRSV_AFE_3_RXDATA_P                          ( TRSV_AFE_3_RXDATA_P ),
   .TRSV_AFE_3_RXDATA_N                          ( TRSV_AFE_3_RXDATA_N ),
   .TRSV_AFE_3_TXDATA_P                          ( TRSV_AFE_3_TXDATA_P ),
   .TRSV_AFE_3_TXDATA_N                          ( TRSV_AFE_3_TXDATA_N ),

   .TRSV_AFE_4_RXDATA_P                          ( TRSV_AFE_4_RXDATA_P ),
   .TRSV_AFE_4_RXDATA_N                          ( TRSV_AFE_4_RXDATA_N ),
   .TRSV_AFE_4_TXDATA_P                          ( TRSV_AFE_4_TXDATA_P ),
   .TRSV_AFE_4_TXDATA_N                          ( TRSV_AFE_4_TXDATA_N ),

   .TRSV_AFE_5_RXDATA_P                          ( TRSV_AFE_5_RXDATA_P ),
   .TRSV_AFE_5_RXDATA_N                          ( TRSV_AFE_5_RXDATA_N ),
   .TRSV_AFE_5_TXDATA_P                          ( TRSV_AFE_5_TXDATA_P ),
   .TRSV_AFE_5_TXDATA_N                          ( TRSV_AFE_5_TXDATA_N ),

   .TRSV_AFE_6_RXDATA_P                          ( TRSV_AFE_6_RXDATA_P ),
   .TRSV_AFE_6_RXDATA_N                          ( TRSV_AFE_6_RXDATA_N ),
   .TRSV_AFE_6_TXDATA_P                          ( TRSV_AFE_6_TXDATA_P ),
   .TRSV_AFE_6_TXDATA_N                          ( TRSV_AFE_6_TXDATA_N ),

   .TRSV_AFE_7_RXDATA_P                          ( TRSV_AFE_7_RXDATA_P ),
   .TRSV_AFE_7_RXDATA_N                          ( TRSV_AFE_7_RXDATA_N ),
   .TRSV_AFE_7_TXDATA_P                          ( TRSV_AFE_7_TXDATA_P ),
   .TRSV_AFE_7_TXDATA_N                          ( TRSV_AFE_7_TXDATA_N ),

   .BKP_IN_TXFP8K                                ( BKP_TXFP8K ),
   .BKP_IN_TXDATA_0                              ( BKP_TXDATA_0[15:0] ),
   .BKP_IN_TXDATA_1                              ( BKP_TXDATA_1[15:0] ),
   .BKP_IN_TXDATA_2                              ( BKP_TXDATA_2[15:0] ),
   .BKP_IN_TXDATA_3                              ( BKP_TXDATA_3[15:0] ),

   .BKP_OUT_RXFP8K                               ( BKP_OUT_RXFP8K ),
   .BKP_OUT_RXDATA_0                             ( BKP_OUT_RXDATA_0[15:0] ),
   .BKP_OUT_RXDATA_1                             ( BKP_OUT_RXDATA_1[15:0] ),
   .BKP_OUT_RXDATA_2                             ( BKP_OUT_RXDATA_2[15:0] ),
   .BKP_OUT_RXDATA_3                             ( BKP_OUT_RXDATA_3[15:0] )
   );

wire                                             tsoh_in_fp;
wire[63:0]                                       tsoh_in_data;
(* keep = "TRUE" *) reg[2:0]                     tsoh_in_fcnt8;
(* keep = "TRUE" *) reg[8:0]                     tsoh_in_fcnt270;
(* keep = "TRUE" *) reg[3:0]                     tsoh_in_fcnt9;

  assign tsoh_in_fp          = BKP_OUT_RXFP8K;
  assign tsoh_in_data[63:0]  = {BKP_OUT_RXDATA_0[15:0], BKP_OUT_RXDATA_1[15:0], BKP_OUT_RXDATA_2[15:0], BKP_OUT_RXDATA_3[15:0]};
always @( posedge GTM_CLK155M ) begin
   if ( tsoh_in_fp==1'b1 )
      tsoh_in_fcnt8[2:0]                                <= 3'd1;
   else begin
      tsoh_in_fcnt8[2:0]                                <= tsoh_in_fcnt8[2:0] +3'd1;
   end
end
always @( posedge GTM_CLK155M ) begin
   if ( tsoh_in_fp==1'b1 )
      tsoh_in_fcnt270[8:0]                              <= 9'd0;
   else if ( tsoh_in_fcnt8[2:0]==3'd7 ) begin
      if ( tsoh_in_fcnt270[8:0]==9'd269 )
         tsoh_in_fcnt270[8:0]                           <= 9'd0;
      else
         tsoh_in_fcnt270[8:0]                           <= tsoh_in_fcnt270[8:0] +9'd1;
   end
end
always @( posedge GTM_CLK155M ) begin
   if ( tsoh_in_fp==1'b1 )
      tsoh_in_fcnt9[3:0]                                <= 4'd0;
   else if ( tsoh_in_fcnt8[2:0]==3'd7 && tsoh_in_fcnt270[8:0]==9'd269 ) begin
      if ( tsoh_in_fcnt9[3:0]==4'd8)
         tsoh_in_fcnt9[3:0]                             <= 4'd0;
      else
         tsoh_in_fcnt9[3:0]                             <=tsoh_in_fcnt9[3:0]  +4'd1;
   end
end


OH_TSOH               INST_OH_TSOH(
   .RESET             ( GTM_RESET ),
   .TCLK_155M         ( GTM_CLK155M ),

   .MPI_TXJ0_DATA     (  ),
   .MPI_TXJ0_MODE     (  ),
   .MPI_TXK1K2        (  ),
   .MPI_TXS1          (  ),
   .MPI_TX_SOH_LOOP_EN(  ),
   .RSOH_B2_CNT       (  ),
   
   .DBIN_TDATA        ( tsoh_in_data[63:0] ),
   .DBIN_FCNT8        ( tsoh_in_fcnt8[2:0] ),
   .DBIN_FCNT270      ( tsoh_in_fcnt270[8:0] ),
   .DBIN_FCNT9        ( tsoh_in_fcnt9[3:0] ),
   .DBIN_MFCNT64      (  ),

   .TSOH_TDATA        ( oh2frm_tdata[63:0] ),
   .TSOH_FCNT8        ( oh2frm_fcnt8[2:0] ),
   .TSOH_FCNT270      ( oh2frm_fcnt270[8:0] ),
   .TSOH_FCNT9        ( oh2frm_fcnt9[3:0] ),
  // data bus from receive side, used for SOH loop
   .RX_RCLK155M       (  ),
   .RX_DBIN_FAS_FAIL  (  ),
   .RX_DBIN_FCNT8     ( ),
   .RX_DBIN_FCNT270   (  ),
   .RX_DBIN_FCNT9     ( ),
   .RX_DBIN_DATA      (  )
   );

 
///assign RXN_IN[7:0] = {DATA_XC2_TO_OLBN[3],DATA_XC2_TO_OLBN[2],DATA_XC2_TO_OLBN[1],DATA_XC2_TO_OLBN[0],DATA_XC1_TO_OLBN[3],DATA_XC1_TO_OLBN[2],DATA_XC1_TO_OLBN[1],DATA_XC1_TO_OLBN[0]};
///assign RXP_IN[7:0] = {DATA_XC2_TO_OLBP[3],DATA_XC2_TO_OLBP[2],DATA_XC2_TO_OLBP[1],DATA_XC2_TO_OLBP[0],DATA_XC1_TO_OLBP[3],DATA_XC1_TO_OLBP[2],DATA_XC1_TO_OLBP[1],DATA_XC1_TO_OLBP[0]};
///
///assign DATA_OLB_TO_XC2P[3] = TXP_OUT[7];
///assign DATA_OLB_TO_XC2P[2] = TXP_OUT[6];
///assign DATA_OLB_TO_XC2P[1] = TXP_OUT[5];
///assign DATA_OLB_TO_XC2P[0] = TXP_OUT[4];
///assign DATA_OLB_TO_XC1P[3] = TXP_OUT[3];
///assign DATA_OLB_TO_XC1P[2] = TXP_OUT[2];
///assign DATA_OLB_TO_XC1P[1] = TXP_OUT[1];
///assign DATA_OLB_TO_XC1P[0] = TXP_OUT[0];
///
///assign DATA_OLB_TO_XC2N[3] = TXN_OUT[7];
///assign DATA_OLB_TO_XC2N[2] = TXN_OUT[6];
///assign DATA_OLB_TO_XC2N[1] = TXN_OUT[5];
///assign DATA_OLB_TO_XC2N[0] = TXN_OUT[4];
///assign DATA_OLB_TO_XC1N[3] = TXN_OUT[3];
///assign DATA_OLB_TO_XC1N[2] = TXN_OUT[2];
///assign DATA_OLB_TO_XC1N[1] = TXN_OUT[1];
///assign DATA_OLB_TO_XC1N[0] = TXN_OUT[0];
///
///
///gtwizard_v2_4_exdes U_gtwizard_v2_4_exdes
///(
///    .Q0_CLK1_GTREFCLK_PAD_N_IN      (MGTREFCLK0_112N),
///    .Q0_CLK1_GTREFCLK_PAD_P_IN      (MGTREFCLK0_112P),
///    .Q1_CLK1_GTREFCLK_PAD_N_IN      (MGTREFCLK0_113N),
///    .Q1_CLK1_GTREFCLK_PAD_P_IN      (MGTREFCLK0_113P),
///    .DRP_CLK_IN                     (clk50m),
///    .SYSCLK_IN                      (clk155m_sys),
///    .TRACK_DATA_OUT                 (track_data_out),
///    .RXN_IN                         (RXN_IN[7:0]),
///    .RXP_IN                         (RXP_IN[7:0]),
///    .TXN_OUT                        (TXN_OUT[7:0]),
///    .TXP_OUT                        (TXP_OUT[7:0])
///);
/// 
// ***********************************************************************
// ENDMODULE
// ***********************************************************************

endmodule 